A High Static Noise Margin Reconfigurable Shift Register File for Cryptographic Chip Using 14T Isolated Cell and Embedded Shift Network

To address cryptographic chips’ requirements for high parallelism, robust stability, and flexible operation, this paper proposes a novel multi-port reconfigurable shift register file (RSRF). It adopts an enhanced 14-transistor (14T) memory cell and differential read circuit to boost noise immunity, with optimized transistor sizing to enhance speed while preserving stability. An integrated configurable shift network allows flexible switching between storage mode and multiple shift operations. Post-layout simulation in 40 nm CMOS at 1.1 V and 25 °C demonstrates a maximum frequency of 2.3 GHz, power consumption of 4.69 mW, and a core area of 0.021 mm2. Compared to prior designs, the proposed architecture delivers high performance and multi-port access while enhancing noise margin and process robustness. By integrating in-memory computing, this work offers a new approach toward efficient cryptographic hardware.