An efficient and simple VLSI tree architecture for motion estimation algorithms

A low-latency, high-throughput tree architecture is proposed. This architecture implements both the full-search block-matching algorithm and the three-step hierarchical search algorithm in motion estimation. Owing to the simple and modular properties, the proposed architecture is suitable for VLSI implementation. Furthermore, it can be decomposed into subtrees to reduce hardware cost and pin count. The memory interleaving and the pipeline interleaving are also employed to enhance memory bandwidth and to use the pipeline 100%. Theoretical calculations and simulation results are presented to show the attractive performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>