Device simulation study demonstrates energy-efficient on-chip unsupervised learning in spiking neural networks, highlighting reduced transistor counts and low-latency synaptic plasticity.
In this paper, we propose an energy-efficient Ge-based device that enables on-chip unsupervised learning using Spike-Timing-Dependent-Plasticity (STDP) in a Spiking Neural Network (SNN). A Ferromagnetic Domain Wall (FM-DW) based device, which has decoupled read and write paths, is used as a synapse in this work. The proposed device comprises a dual pocket Fully-Depleted Silicon-on-Insulator (FD-SOI) MOSFET with dual asymmetric gates. Using a well-calibrated 2D device simulation model, we show that a pair of such devices can generate a current, which depends exponentially on the temporal correlation of spiking events in the pre- and post-neuronal layer. This current is fed to the FM-DW synapse, which in turn modulates the conductance of the synapse in accordance with the STDP learning rule. The proposed implementation requires 2-3× fewer transistors and offers a lower latency compared to existing literature. We further demonstrate the application of the proposed device at the system-level to train an SNN to recognize handwritten digits in the MNIST dataset and obtained a classification accuracy of 84%.
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Gupta et al. (2023) studied this question.
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