Present VLSI technology can integrate up to several hundred neurons with fully connected synapses on a single chip, a number insufficient to realize a practical neural network system. The chip reported here uses I.Om CMOS technology to integrate 336 neurons and 28k synapses, equivalent to 56k symmetrical connections. The chip uses branch-neuron unit (BNU) architecture. Interconnection of 200 chips is believed possible with this BNU architecture, based on the assumption of a 30% firing rate and 1% fluctuation of each neuron unit. Interconnection of 200 chips realizes a neural network system with almost 3,300 neurons and 5.6M synapses (11.2M symmetrical connections).
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Arima et al. (1991) studied this question.
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