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Large language models (LLMs) are increasingly adopted for Verilog code generation, yet existing benchmarks assume English-only prompts, overlooking the linguistic diversity of the global FPGA engineering community. We introduce Multi-VerilogEval, the first multilingual Verilog benchmark, built from 156 unique underlying tasks instantiated in four languages (English, Japanese, Hindi, and Mongolian), yielding 624 language-specific test cases. Our evaluation of four representative LLMs reveals a silent failure pattern: syntactic correctness remains high (∼90%) across languages, but functional correctness degrades by up to 23.9% for non-English prompts in open-source and domain-specific models, while commercial models remain near-parity. Hidden-state analysis suggests that multilingual bias is associated with persistent cross-lingual representation divergence throughout the network, which becomes most pronounced in the final layers that directly drive token generation. As fine-tuning and common prompt-based mitigations remain impractical or unreliable for multilingual RTL, we propose HE-ICL (Hard-Example In-Context Learning), a train-free method that constructs few-shot hard-example demonstrations from cross-lingually difficult cases. HE-ICL closes 80–100% of the multilingual gap without any parameter updates, achieving near-parity with or exceeding the English reference level across all evaluated HE-ICL settings.
Guang Yang (Mon,) studied this question.