Stable and efficient reduction of substrate model networks using congruence transforms

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal cross talk through the common chip substrate has become increasingly problematic. This paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Padé approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples. 1