Synthesis of multiple bus/functional unit architectures implementing neural networks

An automated architectural synthesis methodology for implementing digital neural networks is presented. The synthesis approach uses heuristics and is based on VLSI multiple-bus/functional-unit architectures with internal parallelism. The synthesis methodologies and tradeoffs as well as the features of the architectures are presented. The architectures resulting from the synthesis tool outperform other architectures for the same applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>