Adaptive circuits for the 0.5-V nanoscale CMOS era

The V min s of logic, SRAM, and DRAM blocks were compared with a newly proposed methodology for evaluating V min based on speed variations, taking repair techniques into account. State-of-the-art 6T SRAM cells were then discussed in terms of V min and cell size. After that, many adaptive circuits and relevant technologies needed to break the 1V wall were proposed and evaluated, while taking the interconnect problem into account. Finally, 0.5 V nanoscale LSIs including mixed signal LSIs were predicted to be feasible, if relevant devices and fabrication processes are developed.