Answers are grounded in this paper and cite their sources.
A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.
No takes yet. Share an insight, caveat, or question.
Zhang et al. (2005) studied this question.
Synapse has enriched one closely related paper. Consider it for comparative context: