Integration of III–V materials and Si-CMOS through double layer transfer process

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A method to integrate III–V compound semiconductor and SOI-CMOS on a common Si substrate is demonstrated. The SOI-CMOS layer is temporarily bonded on a Si handle wafer. Another III–V/Si substrate is then bonded to the SOI-CMOS containing handle wafer. Finally, the handle wafer is released to realize the SOI-CMOS on III–V/Si hybrid structure on a common substrate. Through this method, high temperature III–V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damage to the CMOS layer is avoided.