Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

Achieving a power envelope of few milliwatts combined with tight performance constraints is emerging as one of the key challenges for battery-powered and low cost Internet-of-things (IoT) end-nodes. IoT devices have to cope with highly time-varying workloads, characterized by intermittent “race-to-sleep” bursts of compute-intensive operations mingled with long periods of low activity. Architectural heterogeneity provides a possible solution to harmonize these competing constraints; the availability of diverse cores optimized for diverse tasks, but able to run the same code is advantageous for IoT devices. In this paper, we introduce Zero-riscy and Micro-riscy, two novel RISC-V cores targeting mixed arithmetic/control applications and control-oriented tasks respectively. We compare them with the DSP-enhanced open-source Riscy core 1. Zero-riscy is 2.2× smaller than Riscy and provides a 2× energy boost for mixed control/arithmetic code with limited DSP. Micro-riscy is 1.6× smaller than Zero-riscy (∼11.6 kgates in UMC 65nm), has a power envelope of just 100μW at 160MHz and it is 1.4× more energy efficient than Zero-riscy on pure control code.