DRAM variable retention time

A DRAM bit has variable retention time (VRT) when the memory cell leakage, which determines how long a cell can retain information, varies with time. This paper reports on a study of VRT in cells from 4Mbit and 16 Mbit DRAM chips produced by a variety of manufacturers and in a number of technologies including trench capacitor and stacked capacitor cells. VRT cells were found on all chips. This paper describes the detection and characterization of two classes of VRT cells: 2-state and multi-state VRT cells, and presents a model containing 4 activation energies and 3 pre-factors that describes the temperature dependence of retention times and transition rates for the 2-state VRT cells. A description of new test techniques and the analysis needed to detect and study VRT are provided as well as examples from typical 4 Mbit chips.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>