6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

3D stacking and computational imaging are two major driving forces for CMOS image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with sensor circuits while leveraging advanced CMOS technologies including FinFET. To accommodate this trend, we need to design blocks such as comparators, readouts, transmitters, and PLLs, using digital architectures in logic processes with a minimum number of resistors and capacitors.