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September 13, 2016IEEE Journal of Solid-State Circuits

An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS

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Authors

YSYun-Shiang ShuLKLiang-Ting KuoTLTien-Yu LoSarawak Biodiversity Centre

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Shu et al. (2016) studied this question.

synapsesocial.com/papers/6a1aefbb49c3147e104612c2https://doi.org/10.1109/jssc.2016.2592623
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