Calculating Capacitive and Inductive Matrices of Printed Circuit Board Interconnects Using Partial Element Equivalent Circuit Method

This paper presents a developed algorithm for calculating the capacitive and inductive matrices of Partial Element Equivalent Circuit models, applicable to both twodimensional and three-dimensional geometric structures. The algorithm was validated using geometric models of transistor package mounting pads and two- and 8 -wire transmission lines. The results obtained with the proposed algorithm were compared with those calculated in TUSUR.EMC and ANSYS simulation tools. Maximum discrepancies of 5.6 % and 14.7 % were observed for the diagonal and off-diagonal elements of the capacitance matrix calculated for the SOT-23-3 transistor case mounting pad model, respectively. For the transmission lines, the maximum deviations were 1.0 % and 0.2 % for the diagonal and off-diagonal elements of the inductance matrix, respectively. The developed algorithm can be used to analyze interconnects during the design of printed circuit boards, achieving acceptable accuracy in the calculation of capacitive and inductive matrices.