Invited: Coping with Interconnects

In this paper, I review the multi-decade research on overcoming the performance bottleneck of VLSI interconnects in deep sub-micrometer and nanometer technologies that started at UCLA in the early 1990s. Our research spans from interconnect topology and geometry optimization, to wire length reduction via scalable placement, to use of novel interconnect technologies such as 3D IC and RF-interconnects, to recent work on interconnect pipelining in chiplet designs, and the shift from interconnect to entanglement in quantum computing. The latter two efforts go beyond the typical physical design space and involve space-time co-optimization. This paper is dedicated to multiple generations of Ph.D. students, postdocs, and visiting researchers who contributed to build a strong physical design research program at UCLA.