In this paper we have analyzed and modeled the failure probabilities (access time failure, read/write stability failure, and hold stability failure in the stand-by mode) of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip designed with a cell is proposed based on the cell failure probability. The developed method can be used in the early stage of a design cycle to optimize the design for yield enhancement.
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Mukhopadhyay et al. (2004) studied this question.
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