PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
December 22, 200335 citations

A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

View Full Paper
AAAtila AlvandpourRKRam KrishnamurthyDED. Eckerbert

Key Points

Key points are not available for this paper at this time.

Abstract

A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7/spl times/ frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110/spl deg/C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300/spl mu/W at clock gate-off, zero-cycle response during clock re-enable, and <4% static phase error.

Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Alvandpour et al. (2003) studied this question.

synapsesocial.com/papers/6a1c4697ea84844e355fad18https://doi.org/10.1109/isscc.2003.1234230
Ask AI
Helpful
Bookmark
Share
View Full Paper