A Simulated Annealing-Based Approach to Three-Dimensional Component Packing

This paper introduces a simulated annealing-based approach to three-dimensional component packing that employs simulated annealing to generate optimal solutions. Simulated annealing has been used extensively for two-dimensional layout of VLSI circuits; this research extends techniques developed for two-dimensional layout optimization to three-dimensional problems which are more representative of mechanical engineering applications. This research also provides a framework in which to solve general component layout problems.