Triple-Level-Cell/Single-Level-Cell Mix-Mode Operation Induced Data Retention Degradation in 3-D NAND Flash Memories

Compared to single-level-cell (SLC) mode operation, triple-level-cell (TLC) mode operation reduce NAND Flash lifetime due to its stronger program <tex-math notation="LaTeX">$/$ </tex-math> erase ( <tex-math notation="LaTeX">P/E </tex-math> ) cycled-induced oxide degradation and narrower read margin between neighboring states. However, by measuring the evolution characteristics of raw bit error rate (RBER) and threshold voltage ( <tex-math notation="LaTeX">Vₜ </tex-math> ) shift during retention bake, TLC-erase <tex-math notation="LaTeX">$/$ </tex-math> SLC-program mix-mode <tex-math notation="LaTeX">P/E </tex-math> sequences in 3-D NAND Flash memory exhibits significant retention deterioration compared with pure TLC-mode <tex-math notation="LaTeX">P/E </tex-math> schemes. Based on our measurement results, mix-mode operation may create more residual holes in the inter-gate spacing (IGS) region, giving rise to enhanced lateral migration of trapped charge in silicon nitride (SiN) storage layer and the larger <tex-math notation="LaTeX">Vₜ </tex-math> retention loss accordingly.