A > 70dB Digital Readout Circuit Implemented in 65nm CMOS for 10 μ m SWIR InGaAs Pixels

This paper presents a 10 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ mx10μ m</tex> pixel readout interface for SWIR imagers implemented in a 65 nm CMOS technology. The pixel uses a pulse-frequency modulation ADC operating in two steps: a 5-bit coarse conversion and a 7-bit residue conversion. The residue conversion results to a non-uniform quantization that enables an area-efficient implemen-tation without a huge penalty to the system SNR. To improve analog readout performance, digital circuits inside the pixel were removed and transferred as an array mirroring the pixel array in the periphery. This allows for better analog circuitry that requires more area. Address-event representation is used for communication between the two arrays. The power consumption at the maximum expected input current is 0.188 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ W</tex> per pixel. With a full-well capacity of 59.24 ke-, the dynamic range is 74.56 dB, and the linearity error is 0.21 %.