A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques

In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A * VDDmin for low-voltage applications. This L7T features an area-efficient cell layout and a read-disturb free decoupled 1T read port (RP) capable of providing a wide space for write margin improvement. The RBL-EXPD employs (1) boosted RBL (BRBL), (2) 1T-RP with asymmetric-V TH , (AV-1TRP) and (3) offset cell-VDD biasing (OFS-CVDD) to expand RBL swing in both the upward and downward directions securing both `High' and `Low' sensing margins. A 65 nm 256-row 32 Kb L7T SRAM macro-fabricated using BRBL and AVTH-RP achieved a 260 mV VDDmin. The resulting A * VDDmin is ~50% lower than that of conventional 8T SRAM devices.