A 1-GIPS Josephson data processor

A 4-b data processor with 16-instruction set and 1-kb external-RAM access capability has been designed, fabricated, and tested. Each instruction is treated by a three-stage pipeline of instruction fetch, data fetch, and decode/execute. The chip is operable under a 1-GHz clock, and it has a peak performance of 1 GIPS. The fabrication process is 2.5- mu m-rule Nb/AlO/sub x//Nb. An interface circuit to access the all DC-powered 1-kb external-RAM chip is installed. The AC power is utilized with both polarities in each of the four blocks, thus realizing an eightfold serial power supply. Power consumption is 40 mW. Half of the function tests have been completed at low frequency (10 kHz). Part of the processor operated at 1 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>