A novel dc-powered flip-flop logic and/or memory element utilizing two Josephson tunneling gates has been designed and tested. Circuit resistances R, critical currents Ic, and fanout inductances L are chosen so that the gates operate individually in the latching current-steering mode. However, the gates G1 and G2 are interconnected in such a way that if, say, G1 is atV≠0and G2 is at V=0, a switching of G2 toV≠0returns G1 to the V=0 state. The fanout current redistribution, which accompanies this switching event, occurs with a time constant of about L/R. Switching back to the initial state is a symmetric process. Tolerances on circuit parameter values for proper operation are reasonably wide.
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Hebard et al. (1979) studied this question.
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