Memory latency effects in decoupled architectures

Decoupled computer architectures partition the memory access and execute functions in a computer program and achieve high performance by exploiting the fine-grain parallelism between the two. These ar-chitectures make use of an access processor to perform the data fetch ahead of demand by the execute process and hence are often less sensitive to memory access de-lays than conventional architectures, Past performance studies of decoupled computers used memory systems that are interleaved or pipelined. We undertake a sim-ulation study of the latency effects in decoupled com-puters when connected to a single, conventional, non-interleaved data memory module so that the effect of decoupling is isolated from the improvement caused by interleaving. We compare decoupled computer perfor-mance to single processors with caches, study the mem-ory latency sensitivity of the decoupled systems, and also perform simulations to determine the significance of data caches in a decoupled computer architecture. The Lawrence Livermore Loops and two signal process-ing algorithms are used as the simulation benchmark.