Three-dimensional effects in CMOS latch-up

The influence of three-dimensional effects on latch-up in n well CMOS circuits fabricated on both bulk and p on p+ epitaxia substrate material is reported. It is demonstrated that narrow-width phenomena can play a dominant role in determining the latch-up performance of CMOS devices, and give rise to large deviations from ideal scaling with width. This limits the applicability of two-dimensional models, and also means that the latch-up behavior of real circuits may differ significantly from predictions based on the performance of test structures. A simple approach to modeling the three-dimensional phenomena is also presented.