The dynamics of latchup turn-on behavior in scaled CMOS

This paper presents the dynamics of latchup turn-on behavior in scaled CMOS structures using an exact time-dependent and two-dimensional numerical analysis based on the finite-difference approach. Both the dynamics of surface-induced latchup triggering by a parasitic PMOSFET and direct forward biasing are examined to discuss the two-dimensional effects of parasitic devices in a scaled CMOS structure during latchup turn-on. In the case of an n-well scaled CMOS, the two-dimensional nature of the well structure plays an important role for surface-induced latchup.