Latchup-free CMOS structure using shallow trench isolation

Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and the epitaxial layer thickness is 2 µm, the latchup holding voltage, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> is higher than 13 V. The mechanism of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> increase is discussed using an equivalent circuit including the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow with the trench contributes to V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> increase. From the results, it is well expected that the only about 1 µm deep trench must be adequate for achieving V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</inf> higher than the supply voltage, i.e. 5V, and that the fabrication process of trench isolation becomes more reliable and easier.