An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K

In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm Fin Field-Effect Transistors (FinFETs)-based Static Random-Access Memory (SRAM) cells. To perform the SRAM Vmin evaluation, we have measured the FinFETs fabricated using a commercial 5 nm technology down to 10 K. Next, we calibrate a cryogenic aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types - (i) high-density cell (HDC), (ii) low-voltage cell (LVC), and (iii) high-performance cell (HPC). We analyze the impact of the threshold voltage (VTH) and Gate Length (LG)-only variations on the SRAM noise resilience. At cryogenic temperatures minimum-read voltage (Vmin,R) = 0.15V (62% decrease from room temperature) and minimum-write voltage (Vmin,W) = 0.45V is achieved without read/write assist circuits. We also highlight that the LVC cell provides the best trade-off for Vmin between read and write operations for low-power cryogenic applications.