A 23.6-Mb/mm <tex-math notation="LaTeX">² </tex-math> SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications

A 23.6-Mb/mm 2 and a 20.4-Mb/mm 2 SRAM arrays are manufactured in a 10-nm FinFET CMOS technology, utilizing high-density 0.0312 μm 2 and low-voltage 0.0367 μm 2 6T SRAM bitcells. A pulsed-pMOS transient voltage collapse (PP-TVC) write assist circuit is implemented to minimize write energy overhead of the TVC write assist technique, delivering 43% write energy reduction compared to the conventional strong-bias nMOS TVC (SBN-TVC). PP-TVC also achieves up to 50-mV write V MIN reduction at 90th percentile, enabling 0.6-V V MIN for the low-voltage 6T SRAM cell (LVC). A stepped-wordline (S-WL) technique is implemented to deliver >100-mV reduction in the high-density 6T SRAM cell (HDC) write V MIN relative to static WL underdrive (WLUD), while achieving similar read V MIN , pulling the HDC V MIN within 35 mV of the LVC V MIN .