Terman Method to Study Threshold Voltage Hysteresis of Si/SiGe Heterostructures at Cryogenic Temperatures

Semiconductor device reliability at cryogenic temperatures has emerged as an important research area driven by quantum computing applications. Si/SiGe heterostructures have established themselves as a leading platform for quantum devices, yet charge trapping at interfaces remains a key reliability concern. This work presents a phenomenological approach to characterize interface trapping in Si/SiGe heterostacks using fixed charge approximations. We demonstrate that threshold voltage hysteresis observed in capacitance-voltage measurements from 4.2 K to 80 K can be accurately modeled by assigning fixed charges at each channel interface. By combining this methodology with the Terman method, we extract the trap energy distribution, revealing a peak located approximately 0.1 eV below the conduction band with a maximum density of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5 × 10¹² cm⁻² eV⁻¹</tex>. The extracted distributions show strong agreement with interface trap density of states reported in literature, supporting the hypothesis that fast-responding interface traps are the primary mechanism driving the observed hysteresis.