Design and characterization of CMOS APS imagers with two different technologies

In the paper, we present experimental results from measurements on CMOS PAS imager designed by CIMI-SUPAERO on two different technologies. In both cases, pixels with photoMos and photodiode structures have been designed. The first circuit has been developed using a standard CMOS DLP/DLM 1.2 micrometers process from Austria Micro Systems. The detector array consists of 32 X 32 square pixels with 50 micrometers pixel pitch; fill factor is 75 percent for photodiode and 50 percent for photoMos. The circuit is also including row and column address decoders and the readout circuitry so as to perform on-chip correlated double-delta sampling to reduce column to column fixed pattern noise. Two other chips have been developed with a standard CMOS SLP/DLM process form MIETEC with 0.7 micrometers design rules, which includes a 128 X 128 pixels array, with 21 micrometers pixel pitch and analogue redout circuitry. Among 10 different arrays, no faulty one was observed for both circuits. In this paper, we compare both performances of 32 X 32 pixels and 128 X 128 pixels in terms of dark current, quantum efficiency, conversion gain, dynamic range, linearity and spatial uniformity.