Shuttling Compiler for a Trapped-Ion Quantum Computer Architecture with Junctions

Current trapped-ion quantum computer architectures based on segmented traps utilize shuttling operations to establish connectivity between multiple sub-registers within one quantum processing unit. Complex trap architectures, including racetrack loops and junctions, offer prospects for increased scalability and have been successfully built and demonstrated. As hardware capabilities evolve, the need arises for additional automated software layers within the control stack for managing qubit routing. We present the automated generation of shuttling schedules for a branched ID architecture within a shuttling compiler that requires the integration of junctions. This not only provides the means for leveraging future new hardware advances, but also allows guiding the development of future architecture via resource estimation. Testing a wide range of quantum circuits, the junction-enabled shuttling compiler is able to reduce the necessary operations by a factor > 50 for translations and > 20 for separation/merge as compared to a linear architecture.