An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration

Classification of highly dimensional Microarray data using K-nearest neighbour (K-NN) is a time-consuming task when implemented on general purpose processors (GPPs), and such it can benefit greatly from a parallel hardware implementation. In this work, an FPGA implementation of the K-NN classifier is presented and compared with an equivalent implementation running on GPP. Then, a novel FPGA-based multi-core implementation of the K-NN ensemble classifier, which exploits dynamic partial reconfiguration (DPR) is presented. The FPGA implementation of the single core K-NN classifier was found to be 92× faster than a GPP implementation, and the ensemble implementation was found to offer ~5× speed-up of the FPGA reconfiguration time. In addition, the paper investigates the effect of data dimensionality on classification time on both FPGAs and GPPs, showing that FPGAs scale up better than GPPs with higher data dimensionality.