2-D mesh has been widely used as an on-chip network topology, because of its low design complexity and physical scalability.However, its poor latency and throughput scaling have been well-noted in the past.Previous solutions to overcome its unscalability relied on outdated assumptions that no longer hold true in recent architectures.Concentrated routers make an assumption that low injection rate would cause low conflicts; however, recent manycore processors and accelerators require streaming bandwidth for their data-intensive workloads.Widening the channel width to recover the bisection bandwidth halved by concentration assumes that the underlying architecture can flexibly adapt to the wider channel width; however, it comes with an additional cost associated with wider datapaths, serialization, and additional buffering.Ruche Networks retain all the desirable properties of 2-D mesh to remain physically scalable, yet provide an architecturally flexible and cost-effective mechanism to effortlessly scale up the network performance by adding uniform long-range physical links.While their feasibility in real silicon has been demonstrated, there has not been any detailed evaluation of its network performance, scalability, and energy efficiency.This paper aims to fill the gap in research by providing some insight on design tradeoffs.Using RTL-level implementations, we demonstrate that Ruche Networks are superior to 2-D mesh and torus in terms of power, area efficiency, cycle time and network performance.
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Jung et al. (2025) studied this question.
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