Designing the best clock distribution network

Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an increasing fraction of resources such as wiring, power, and design time. Unwanted differences or uncertainties in clock network delays degrade performance or cause functional errors. Three dramatically different strategies being used in the VLSI industry to address these challenges are compared. Novel modeling and measurement techniques are used to investigate on-chip transmission-line effects that are important for high performance clock distribution networks.