PACE: a dynamic programming algorithm for hardware/software partitioning

This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardware and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n/sup 2//spl middot//spl Ascr/) and the space-complexity is O(n/spl middot//spl Ascr/) where /spl Ascr/ is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software.