Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier

Aim of this paper is to compare and prove implementation of normal multiplication and Vedic multiplication (using Urdhva Tiryakbhyam Sutra) on digital hardware requires same number of multiplication and addition operations.It makes difference only for mental calculations. Few VHDL codes has been developed for this. All multipliers has been tested for 16 × 16 multiplications for comparison. Test vectors has been given through a text file. Implementation has been done for the Xilinx FPGA device, Virtex XCV 300 -6PQ240. Various multiplier implementations such as Array multiplier, Multiplier Macro, Vedic multiplier with full partitioning, Vedic multiplier using 4 bit macro, multiplier using 4 bit macro, fully Recursive Vedic multiplier, Vedic multiplier using 8 bit macro have been tested and compared for optimum area and speed.