Reducing test application time for full scan embedded cores

We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS890 circuits showed that PSFS technique significantly reduces both the test application time and the amount of test data for full scan embedded cores.