A Suppression Method for Filter-Order Burden Based on Asynchronous SAR Quantizer Residue

This paper presents a passive residue-coupled discrete-time delta–sigma (ΔΣ) modulator for low-power narrowband sensing applications. Instead of adding a fourth active integrator, the proposed architecture keeps a third-order switched-capacitor main loop and reuses the intrinsic top-plate residue of an 8-bit asynchronous successive-approximation-register (SAR) quantizer. The retained capacitive digital-to-analog converter (CDAC) residue is passively reinjected through a charge-redistribution path, introducing an additional high-pass error-propagation factor in the effective noise transfer function (NTF). Under a bounded effective coupling coefficient, the proposed loop approaches fourth-order-like in-band noise suppression while retaining third-order active-loop complexity. Behavioral simulations show that the Enhanced mode improves the peak signal-to-noise-and-distortion ratio (SNDR) by 16.9 dB over the Baseline third-order mode at an oversampling ratio (OSR) of 128. Circuit-level corner verification of the standalone SAR confirms correct bit cycling and a settled residue-retention window under typical–typical (TT), slow–slow (SS), and fast–fast (FF) conditions: with the slowest conversion window of about 21.4 ns at the SS corner and a sampling period of 39.06 ns at fs=25.6 MHz, roughly 17.66 ns of timing margin remains for residue holding, passive reinjection, and clock non-overlap. The proposed method provides an architecture-level route for improving in-band noise shaping without increasing the number of active integrator stages, and is particularly attractive for low-power, narrowband, and sensor-oriented analog-to-digital converter (ADC) applications.