Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically reconfigurable interconnects and memory. Versa leverages reconfigurable functional units and systolic-enhanced ARM cores to adapt for different algorithm characteristics, providing optimized bandwidth, access latency, and data reuse. Hardware support for crucial thread-synchronization operations enables a tree-based algorithm with 6.5 <tex-math notation="LaTeX">× </tex-math> improvement in synchronization latency. Measured on a diverse set of compute kernels, Versa’s design features culminate in median energy-efficiency improvements of 37.2 <tex-math notation="LaTeX">× </tex-math> and 11.6 <tex-math notation="LaTeX">× </tex-math> over mobile CPU and GPU baselines, respectively.