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The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word*1-b and 256 K word*4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7- mu m double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 mu m/sup 2/ and a chip size of 86.6 mm/sup 2/. The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times.>
Kohno et al. (Fri,) studied this question.