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Demonstrates improved phase noise in multichannel radar transceivers, highlighting efficiency in power consumption.
This paper presents a highly integrated 60 GHz transceiver for FMCW radar applications realized in a 28 nm bulk CMOS technology. The chip provides two transmit (TX) and three receive (RX) channels. The 60 GHz local oscillator (LO) distribution is fed with the frequency-multiplied signal of the integrated low phase noise 15 GHz voltage-controlled oscillator (VCO). Realized in 28 nm technology node, the proposed chip is able to generate chirp signals over a continuous 57-64 GHz frequency-tuning-range. The phase noise is <; -93 dBc/Hz @ 1 MHz offset. The measured peak phase noise performance is -99 dBc/Hz @1 MHz offset for a 55.5 GHz carrier frequency. The single TX/RX DC power consumptions are 63 mW and 39 mW, respectively. The total DC power dissipation is 478 mW.
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Rimmelspacher et al. (2020) studied this question.
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