Comparative Modeling of Single-Ended Through-Silicon Vias in Gs and GSG Configurations Up to v-Band Frequencies

This work presents a novel comparative modeling scheme for single-ended (SE) through-silicon vias (TSVs) in GSG and GS configurations. Physical scalable models based on the equations developed herein indicate that the use of two symmetric ground TSVs in GSG configuration relatively increases the parasitic capacitance and conductance in the silicon substrate. However, this increase in the parasitic capacitance requires that the parasitic inductance of SE TSV is reduced to maintain the same phase velocity in silicon. According to the modeling results, the GSG configuration has a larger insertion loss than that of the GS configuration because the former has a higher substrate conductance. Nevertheless, when measured using RF coaxial probes, the GSG configuration exhibits a larger measurement bandwidth than the GS configuration. Finally, with the assistance of a double-sided probing system, wideband S-parameter measurement can validate the established equivalent-circuit model of SE TSV in GSG configuration up to V-band frequencies.