Improving Practical Sensitivity of Energy Optimized Wake-Up Receivers: Proof of Concept in 65-nm CMOS

We present a high-performance low-power digital baseband architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65-nm CMOS, the digital baseband consumes 0.9 μW (VDD = 0.37 V) in sub-threshold operation at 250 kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum VDD of 0.23 V at fmax = 5 kHz and 0.018 μW power consumption. Based on these results, we show that our digital baseband can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared with what is traditionally reported.