Two-dimensional stochastic model for interconnections in master slice integrated circuits

Two-dimenslonal stochastic models for Interconnections in master slice LSI are described. Several limit theorems are derived for estimating the wiring area on large chips in terms of average wire length R, average number of wires emanating from each logic block, and wire trajectory parameters. The expected value of the maximum number of tracks per channel on an N N chip is shown to be less than O (N) as long as R does not grow faster than O (N). If R > O (N), then the expected maximum number of tracks is O (R). Simple bounds on the expected wiring area are given and numerical results compared to the earlier work by Helier et al.