Design of type 2 diaital phase-locked loops

The practical importance of digital phase-locked loops in which the phase error should be zero under locked conditions and in which frequency capture is automatically achieved has led naturally to the development of type 2 loops. The optimum design of these essentially non-linear, sampled data systems has led to digital computer studies in both the frequency and time domains. A universal frequency domain design chart is described which allows design for which relatively stable operation over a range of working is guaranteed. The paper includes a worked example and gives elementary rules of thumb for the prediction of settling time and bandwidth.