This paper describes an all-digital on-die true random number generator implemented in 45 nm CMOS technology, with random bit throughput of 4 Gbps and total energy consumption of 0.57 pJ/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use of digital components enables a compact layout occupying 1024 mum 2 with high entropy/bit of 0.94, and scalable operation down to 0.5 V, while passing all NIST RNG tests.
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Srinivasan et al. (2009) studied this question.
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