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A high-performance 32b CMOS microprocessor with an on-chip cache and low power for functional and standby modes has performance of 26MIPS and dissipates only 1.77 W in functional mode. The features include a 16 b data interface and 24 b address bus, a 16 kB four-way set associative cache, and a clock doubler for operation at 33/66 MHz. The chip is 9/spl times/7.7 mm/sup 2/. It uses single-latch LSSD design and has 99.5% stuck-at fault test coverage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Bechade et al. (2002) studied this question.