An Automatic Duty Cycle Corrector for Dual-Edge 24 GS/s RF Sampling Circuit

Sampling clock duty cycle error degrades the performance of downconverting dual-edge sampling systems, requiring correction circuitry to guarantee the optimal duty cycle at the sampling location. This paper derives the theoretical effect of duty cycle errors in such systems and studies the technique of averaging samples to mitigate the problems. The analysis concludes that such a system can be designed in a manner where the duty cycle error causes no non-linearity, and only gain and phase errors. However, even these may result in non-linearity in time-interleaved systems, requiring duty cycle correction. An automatic duty cycle corrector used in a dual-edge downconverting sampling system is demonstrated in this paper. The proposed tuning circuit controls the DC level of the reference clock signal according to the detected duty cycle. The proposed duty cycle detector has automated self-calibration to ensure robustness under process, voltage and temperature variations. The corrector is designed to be used with sampling clock frequencies up to 12 GHz, which results in 24 GS/s in dual-edge sampling. The operation of the corrector is verified in system simulations that demonstrate its capability to reduce the effects of incorrect duty cycle over a wide frequency range of 2–12 GHz. In the simulations, the duty cycle tuner achieves 16–74 % tuning range, while adding less than 40 fs of jitter over the desired tuning range of 40–60 % and consuming 1.05 mW of power at 12 GHz.